The number of functions on a single integrated circuit chip continues to increase in concert with an increase in chip densities. These "system-on-a-chip" integrated circuits typically use a common, shared bus architecture to provide the communication link between the various devices and subsystems of the "computer system." A common bus provides a low cost communication link since it can be shared between multiple devices in the computer system. However, the linking of multiple devices to a single bus may raise concerns over maximum bus performance.
Achieving maximum bus performance may be difficult in a shared bus architecture. Factors which severely impact bus performance include system throughput (i.e., bandwidth) and system response time (i.e., latency). For purposes of determining throughput or bandwidth, a bus transaction is a bus transaction completed by the device which is on the receiving end of the transmission. Throughput or bandwidth is the average number of bus transactions over a period of time. Response time or latency is the time it takes to complete a bus transaction for a particular device beginning with the cycle during which the device first requests the bus until the cycle that the last piece of data is transferred from the device across the bus to a second device. A device which requests access to or control of a bus and transmits and receives data across a bus may be referred to as a "master." A device which transmits or receives data across a bus and is responsive to a master, may be referred to as a "slave." A slave cannot request access to or control of a bus.
In order to achieve a high degree of bus performance, the throughput must be high while the latency must be low. Further, in order to achieve a high level of bus throughput, the slave preferably is never idle and, consequently, the bus is preferably never idle. In contrast, however, since latency refers to the time it takes to complete a bus transaction beginning with the cycle during which a master first requests the bus until the cycle during which the last data is transferred by the master across the bus, latency includes the time during which a master waits for the bus to become available (i.e., idle). As a result, latency is reduced by allowing the bus to be idle.
A number of different architectural designs have been developed in an effort to address bus performance, including throughput and response time. Many of these schemes rely on the "priority" level of the device seeking control of the bus. For example, U.S. Pat. No. 5,438,666 to Craft et al. describes an arbitration system for controlling access to a bus. The arbitration system of Craft et al. interrupts the control of the bus by a first device when a second device having greater priority requests access to the bus. Once the second device completes its access to the bus, control of the bus is returned to the first device. The transfer of control is implemented without requiring the timing overhead of arbitrating priority between bus masters having active bus requests.
U.S. Pat. No. 5,140,680 to Best describes a bus arbitration system for a computer network having multiple master and slave devices which share a common bus. The bus arbitration system includes bus arbitration logic in each master device, and accounts for the slowest master's operational delay when determining which master shall have access to the bus at a given time.
By way of further example, U.S. Pat. No. 5,388,228 to Heath et al. which is assigned to International Business Machines Corporation, the assignee of the present invention, describes an arbitration system having a central arbitration control circuit and a local arbiter associated with each device seeking access to a common bus. Heath et al. also provides for the programming of each device to operate in either a linear mode or a fairness mode. When operating in the fairness mode, a first device having access to the bus in response to a second device requesting bus access will relinquish control of the bus, once the first device has completed an appropriate number of transfers, allowing the requesting device having the next highest priority level to gain control of the bus.
Other designs which involve sharing of a common bus have attempted to address the conflicting design requirements of high throughput and low latency by using long burst transfers to achieve higher throughputs while using master latency timers to reduce latency by limiting the length of the bursts. Latency timers typically may be implemented in a master using a programmable register and a counter. The initial latency count value which represents the maximum number of clock cycles that the master may maintain control or ownership over the common bus is loaded into the programmable register. The counter is typically reset to zero each time the device gains control of the bus. Once the value of the counter reaches the value stored in the register (i.e., the latency timer has expired), the corresponding device having control over the bus must relinquish the control regardless of the system's bus usage conditions.
As a result, in systems where the bus usage is light (i.e., data transfer across the bus is relatively minimal), a device whose latency timer has expired, and consequently, must relinquish control of the bus even though it has additional data to transfer across the bus, has a bandwidth (i.e., throughput) which may be unnecessarily limited. Moreover, in systems where bus usage is relatively high, in that various devices are requesting the bus simultaneously, a device is likely to use the bus until its latency timer expires. One device's control of the bus until its latency timer expires causes other devices to wait for the bus to become available, and consequently, experience relatively high latencies.
Moreover, the bus usage conditions in a system may vary over time from, for example, light usage to heavy usage back to light usage. Consequently, it may be necessary to update each device's latency timer in order to achieve maximum bus performance. A latency time may be updated by reprogramming the register and counter. However, significant overhead is required to reprogram each device's latency timer, particularly if it occurs on a regular basis. Thus, use of latency timers to improve bus performance is generally ineffective due to dynamically changing bus usage conditions.
Although various arbitration schemes or latency timers are presently used to control access to a common bus in multiple device systems, these prior designs may not effectively address the conflicting design requirements of high throughput and low latency. Moreover, these prior designs do not account for dynamically changing bus usage conditions. In order to improve maximum bus performance, the conflicting problems of high throughput and low latency must be addressed while accounting for dynamically changing bus usage conditions.